Voltage regulator



Aug. 17, 1965 Filed April 23, 1962 H. U. HJERMSTAD ETAL VOLTAGE REGULATOR 2 Sheets-Sheet 1 Ila I211 Isa m lam 102 i 40 n f FIG. 3 N t 211 scmascRz I F |o| Lscm i l :03 MI. I LOAD SOURCE SCR2 53 42 #6 53b J I FIG. 4A m r 3.

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I 1 I 2b 0R4 FIG. 4 B I L' l HP W b |3 62 1- 63" l2b I 62b- 6% PM FIG. 4C CLAMP VARIABLE 53 5 53b Wm}- SIGNAL BOOST. SIG.

cmcun so cmcun 60 FIG. 4 D 5m 6m voimcs 72 PF m) 6''), szujon cm F IG. 4E I J 52 1152b l0 FIG. 4F 50122 d con F|G. 4G 630. a 63b M FIG. 4H SCR3 FIG. 4J 53 a 53b V O S F|G 4K Hans U. H ermsrad SCR4 con m BY Rudolf Schumacher.

g- 1955 H. u. HJERMSTAD ETAL 3,201,683

VOLTAGE REGULATOR Filed April 23, 1962 2 Sheets-Sheet 2 FIG; 5

OUTPUT 230V.

IBOV. Z

INPUT/ 8 A FIG. 9A

CUR+RENT i FIG. 9B

Hans U. Hjermstad BY Rudolf Schumacher 'cordance with the invention so as to boost United States Patent 3,291,683 VULTAGE REGULATQR Hans U. Hiermstad, Chicago, and Rudoif Schumacher, Wood Dale, Ill, assignors to Electro-eal Corporation, Des Plaines, EL, a corporation of liilinois Filed Apr. 23, 1962, tier. No. 189,341 @iaims. (El. $23- 45) The present invention relates to regulated power supplies and particularly to a phase controlled constant voltage power supply.

An object of the present invention is to provide a new and improved regulated power supply capable of providing a constant output voltage over a broad range of lesser input voltages.

A more specific object of the invention is to provide a new and unique power supply design including a transformer arranged so as to be substantially non-loading on the line but responsive to an output voltage less than a predetermined maximum for addin a boost voltage to the line voltage.

More specifically, it is an object of the present invention to provide a new and improved voltage regulator including a transformer for which the secondary winding is connected in series with the voltage source and voltage load and the primary winding is connected selectively in parallel with the voltage source and voltage load. In a parallel relationship with the primary winding is a first circuit and in series with the primary winding is a second selectively operated circuit. The first circuit is selectively closed during portions of the cycles of the input voltage thereby shunting the primary winding and preventing a return flow of power from the secondary. The second circuit is selectively operated during the same portions of the cycle for purposes of drawing additional current through the primary winding in such a manner as to generate a boost voltage in the secondary winding that is additive with the voltage in the loop. The amount of boost voltage added is determined by the period during which the second circuit is conducting, and that period is selected to maintain the root mean square voltage at the output at a predetermined level.

Further objects and features of the invention pertain to the particular structure and arrangements whereby the above identified and other objects of the invention are attained.

The invention, both as to its construction and mode of operation, will be better understood by reference to the following specification and drawings forming a part thereof wherein:

FIGURE 1 is a schematic representation, partially in block form, showing a voltage regulator circuit in accordance with the present invention;

FIGURE 2 is a representation ofan alternating current voltage input to the voltage regulator of FIGURE 1;

FIGURE 3 is a representation of the alternating voltage output signal from the Voltage regulator modified in acthereof;

FIGURES 4A to 4H, 41 and 4K, inclusive, are representative of voltage pulses and wave forms occurring within the circuit at specified times and intervals;

FIGURE 5 is a schematic representation of the clamp signal circuit otherwise shown in block'schematio form in FIGURE 1;

FIGURE 6 is a schematic representation of the variable boost signal circuit otherwise shown in block schematic form in FIGURE 1;

FIGURE 7 is a schematic representation of a voltage sensor circuit otherwise shown in block form in FIG- URE 1;

the amplitude 32%,683 Fatented Aug. 17, 1965 FIGURE 8 illustrates the variation in the amplitude of the input alternating voltage signal that is accepted by the voltage regulator in accordance with the invention;

FIGURES 9A and 9B illustrate the range of voltages that may be experienced within the voltage sensor circuit and the corresponding control signal generated thereby.

Giving consideration to the drawings, there is shown in FEGURE l a block schematic of the arrangement in accordance with the present invention. The voltage regulator circuit thereof is identified by the general reference character 10 and is seen to be provided with a source of alternating current'ltl and a load device 30 to be driven from the output or" the voltage regulator 10. As is explained in detail hereinafter, the voltage regulator 19 is adapted to provide a constant output voltage of, for example, 230 volts for an input variation of, for example, from 180 volts to 230 volts. The circuit 1% is provided with a pair of input terminals 11a and 11b to which the alternating current source 29 is connected and is also provided with a pair of output terminals 320: and 12b to which the load device 3%) is connected. Conductors 13a and 13c, and conductor 1312 are in extension between the terminals 13a and 12a, and 11b and 12b, respectively.

The regulator circuit itself is comprised of a transformer T1 including a primary winding TIP and a secondary Winding TiS and a shunt circuit 44 between the conductors 13a and 13b and including the primary winding TlrP of the transformer T1: The secondary Winding T13 is connected in series with the conductors 13a and 13c between the input and output terminals 11a and 12a.

in the shunt circuit d d, the primary winding T 1? is connected in parallel with a pair of silicon controlled rectifiers SCRi and SCRZ, and in series with a pair of parallel connected silicon controlled rectifiers SCR3 and SCR4. A clamping signal circuit 5i) provides gating signals to the control rectifiers SCR1 and SCRZ.

The boost rectifiers SCR3 and SCR4 are triggered from a variable phase firing circuit 60 which is controlled fur ther by a voltage sensor circuit 70.

Giving consideration for a moment to the general operation of the circuit 10, the clamp signal circuit 50 is provided with an input signal from conductors 13a and 1312 via conductors 51a and 51b. The clamp signal circuit 59 operates on the alternating current signal provided thereto to develop across the conductors 52a and 5212 a positive going gating pulse during each positive going half cycle of the alternating current signal and to produce across the conductors 53a and 53b a positive going gating signal on each negative half cycle of the alternating current signal.

The voltage sensor circuit 70 is provided with an input signal from the conductors 13b and via conductors 71a and 71b. The output signal is detected and applied to a standard to provide to conductors 72 and 73 extending to the variable boost signal circuit 60, a signal of such amplitude and polarity as to reduce the error between the detected signal and the standard amplitude if the output signal applied to the conductors 71a and 71b is maximum and to provide on the conductor 72 and 73 a signal of opposite and diminishing amplitude as the signal applied to the conductors 71a and 71b diminishes from rated maximum voltage to rated minimum voltage.

In the variable boost signalcircuit 6d the alternating current signal from the conductors 51a and 51b is transmitted via the conductors 61a and 61b for purposes of normally providing output signals to the conductors 62a and 62b, and 63a and 63b. Specifically, the variable boost signal circuit dtl will, during posiitve half cycles of the alternating current signal, provide a gating signal across the conductors 62a and 62b and during negative half cycles of the alternating current signal provide posiassassa tive going pulses across the conductors 63a and 635. This control is further modified in the variable boost signal circuit 60 so that the signals applied to the output conductors are delayed from zero to 180 of the wave period. This delay is controlled in accordance with the signal provided to the conductors 72 and 73.

Considering now the operation of the circuit of FIG- URE 1 in accordance with the present invention, it is assumed for purposes of explanation that it is preferred to provide a regulated output of 230 volts from an input of 208 volts. Without the silicon controlled rectifier SCRI, SCR2, SCR3 or SCR4 being operative the secondary winding T18 of the transformer T1 will act as an inductance in series with the load 3% and the input 20 and cause a voltage drop until such time as the transformer T1 should saturate. At the same time t1, a flow of current in the forward direction from terminal 11a to terminal 12a will generate in the primary Winding TIP a voltage tending to bias the rectifier SCR2 positive from anode to cathode. Now assuming that the conductors 52a and 52b have on them at that time t1 a gating pulse as shown in FIGURE 4B, the diode SCRZ will be rendered conductive as shown in FIGURE 4F and support a current flow in the loop including the winding TIP, SCR2 and the choke coil 41. Accordingly, the inductance TIS will be unloaded and only a very small voltage drop will be experienced thereacross during the conduction period of SCR2.

If after a period of time subsequent to time t3, the conductors 62a and 6212 have applied thereto a positive going pulse as illustrated in FIGURE 4G, the rectifier SCR3 will be rendered conductive and current will then be permitted to flow in a path from conductor 13a through the primary winding TIP, the choke coil 42.

and the rectifier SCR3 to conductor 13b. At that time the voltage across the primary winding at TIP is reversed so that the silicon controlled rectifier SCRZ is non-conductive. This current flow through the primary winding TIP of the transformer T1 induces a flux into the core of the transformer which generates in the secondary winding TllS a voltage of a polarity cooperating with the voltage drop across the terminals 12a and 12b as indicated in FIGURE 4A, which voltage adds itself to the output curve 101 as a boost 102 as indicated in FIG- URE 3. In this manner, the total output power at the terminals 120 and 12b is increased over that voltage 100 available at the input terminals 11a and 11b as indicated in FIGURE 2. At the beginningof the next half cycle at the time t4, the silicon controlled rectifier SCRl has applied across its gate terminal and cathode via the conductors 53a and 53b a gating signal as indicated in FIG- URE 4C. Atthe same time, the voltage across the primary winding TIP of the transformer Tl'is such as to bias the SCRI positive from anode to cathode and to render the rectifier conductive. This is illustrated in FIGURE 4D. Accordingly, the output wave at the conductors 12a andIZb is substantially unaffected during the time t4 to t5, all as illustrated in FIGURE 3.

, However, at some time during the cycle period between t and t7, and specifically at a time t6, the silicon controlled recitfier SCR4 has applied across its gating terminal and cathode via the conductors 63a and 63!) a positive going gating pulse as illustrated in FIGURE 4]. Accordingly, the silicon controlled rectifier SCR4 is gated for conduction and as the anode to cathode voltage is positive between conductors 13b and 1311 via the choke coil 42 and the primary winding TIP, conduction takes place through the rectifier SCR4 in that path.

This current flow from conductor 13b to conductor 13a through the primary winding TIP of the transformer T1 generates in the secondary winding TIS a Voltage having a polarity cooperating with that already operative between the conductors 13a and 13b, and as shown in FIGURE 4A, so as to produce at the output terminals 12a and 12b the basic wave form fill having it superimposed thereon the voltage pulse 103. In this fashion, any deficiency in the amplitude of the input voltage 100 as shown in FIGURE 2, is boosted so as to provide to the output terminals 12a and 1211 an R.M.S. voltage of the preferred regulated amplitude.

Obviously, in this control it is important to the effect of operation of the circuit that the gating pulses applied to the conductors 52a and 52b and 53a and 5311 by the clamp signal circuit 5t} be in essential synchronism with the start of each alternate half wave cycle period. This is to make certain that the transformer secondary TIS does not act as an impedance during the part of the cycle when no boost voltage is required. Equally important is the operation of the variable boost signal circuit so and the voltage sensor circuit '70 in ultimately furnishing'to the conductors 62a and 62b, and conductors 63a and 63b gating pulses properly timed so as to add to the cycle of each alternate half wave suficient power so as to maintain the R.M.S. voltage at the preferred regulated level.

As shown in FIGURE 5, the clamp signal circuit is composed of a transformer T2 having a center tapped primary winding wherein the lower and upper halves are identified respectively by the identification characters T2PI and T2P2, and separate secondary windings T251 and T282. In parallel with the primary winding are a pair of oppositely posed diodes D53 and D54, joined at their junction by means of a Zener-diode D to the center tap of the primary winding. A transformer T3 is connected in parallel with the primary windings of the transformer T2. Additionally in this arrangement there is included a resistor R56 in series with the input conductor 51a and a current limit resistor R57 in series with the output conductor 52b, and a current limiting resistor R58 in series with the output conductor 53a. In this arrangement the alternating current of reference is applied through the resistor R56 across the primary of the transformer T2. In the instance where the voltage on the conductor 51a is positive with regard to the voltage on the conductor 51b, the diode D53 conducts a current into the zener-diode and into the lower half of the transformer winding T2P1 through the Zener-diode D55. An equal and opposite voltage is generated in the upper half of the winding T2P2 in accordance with normal auto transformer action. The zener-diode establishes a level at which the sine wave is clipped, resulting in a square wave across the primary of transformer T2. By operation of the transformer T3, the square wave is terminated before the cycle goes through zero voltage. The output from the transformer T2 is fed via the secondary windings T281 and T282 through the current limiting resistor R57 and onto the pair of conductors 52a and 52b and through the current limiting resistor R58 to the conductors 53a and 53b. Accordingly, a square wave is generated for each half cycle which rises with the rise in the voltage from zero and is terminated upon saturation of the transformer T3 prior to the half cycle going to zero so as to remove the pulse from the gating electrode and to make certain that the corresponding silicon controlled rectifiers are in condition to become non-conductive.

'The variable boost signal circuit 60 'is shown in greater detail in FIGURE 6. This unit includes essentially a transformer T4 having a primary winding center tapped to provide two individual auto transformer windings "MP1 and T4P2 and individual secondary windings T481 and T482, and a saturable core reactor T5 including control output windings T51 and T54 and control windings T52 and T53. A pair of oppositely poled diodes D64 and D65 are arranged across the primary windings of the transformer T4 and a zener-diode D66 is connected between the center tap of the primary winding in the transformer T4 and thejunction between the diodes D64 and D65; The mode of operation of the resistor R165,

diodes D64, D65 and the zener-diode D66 in producing square wave pulses at the secondary windings T481 and T4S2 is essentially the same as that described above with regard to circuit 50 in FIGURE 5. The square wave pulse developed on the Winding T4S1 is unidirectional and develops a complete current path through the winding T51 of the saturable reactor T5, the diode D67 and the resistor R162. Dependent upon the amount of saturation in the reactor T5, the voltage drop across the resistor R162 will vary.

A similar circuit is completed from the secondary winding T482 through the winding T54 of the reactor T5, diode D68 and resistor R161. Saturation in the saturable reactor T is controlled via the series coupled control windings T52 and T53 which are fed signals via the conductors 72 and 73 extending from the voltage sensor ci-rcuit 70. The output from the variable boost signals circuit 60 depends upon the amount of signal extended via the conductors 72 and 73. Specifically, as the saturable reactor T5 is in a saturated state, current from the secondary winding T431 will pass through the reactor T5 and through the diode D67 substantially without change thereby to provide a corresponding instantaneous voltage drop across the resistor R162. However, if the signal on the conductors 72, 73 should be reduced and the state of the reactor T5 diminished from a saturated state, there will result a condition somewhere between a maximum passage of energy (for the condition of saturation) and no passage of energy (where all of the signal is absorbed). A DC. signal between these limits will result in the reactor saturating somewhere between the start and the finish of the cycle. This signal generated across the resistor R162, is transmitted via the conductors 62b and 62a to the gate electrode and cathode of the silicon controlled rectifier S CR3 and the signal across the resistor R 161 is transmitted via the conductors 63a and 63b to the gate electrode and cathode of the silicon controlled rectifier SCR4.

The nature of the voltage sensor circuit 70 is as shown in FIGURE 7. Specifically, the circuit thereof includes a step-down transformer T6, a bridge rectifier 72a and a resistance zener-diode bridge 79. Input voltage on the conductors 71a and 71b applied to the primary winding T6? of the transformer T6 wherein a step-down voltage is developed across the secondary winding T68 and applied to a resistor 71 to the input terminals 72a and 72b of the diode rectifier bridge 72e. The output at the terminals 72c and 72d is proportional to the R.M.S. voltage of the alternating circuit signal on the terminals 71a and 71b and is applied across the variable resistor 74a and the fixed resistor 74b. The voltage across the resistor 74]) and the tapped portion of the resistor 74a is applied to the bridge 79. The bridge 79 is comprised of a pair of zener-diodes D75 and D76 arranged in opposite arms of the bridge and a pair of resistors R77 and R78 arranged also on opposite arms of the bridge. The conductors 72 and 73 are connected across the output terminals of the bridge. An input signal applied to the conductors 71a and 71b may vary between 180 volts and 230 volts as shown in FIGURE 8.

In the exemplary arrangement of FIGURE 7, the output voltage at the tap of the variable resistor 74a and across the resistor 7412 will correspond closely to the R.M.S. value of the output voltage of the regulator 10. This DC. voltage is applied to the bridge 79 and as long as the DC. voltage is lower than the voltages of the zener-diodes combined, the conductor 72 will be positive with respect to the conductor 73 by an amount equal to the magnitude below 230 volts R.M.S. However, as soon as the DC. voltage exceeds the zener-diodes the polarity of the conductors 72 and 73 reverse. This reversal occurs at an exact standard voltage corresponding to 230 volts R.M.S. and any deviation in voltage from this standard, results in a signal of such polarity and magnitude on conductors 72 and 73 that the output of the regulator tends to be held constant and close to 230 volts R.M.S. Changing the tap on resistor 74a applies a greater or lesser amount of voltage to the standard. Thus efiectively, the regulated output voltage is controlled at the tap of the resistor 74a. Changing the position of the tap changes the amount of DC. voltage applied to the bridge 79. FIGURE 9A shows a range of voltages as may be experienced across the input terminals of the bridge 79, with FIGURE 9B illustrating the reaction that will take place across the conductors 72 and 73 when the input voltage hits the breakdown voltage B of the zener-diodes D and D76. From FIGURE 913 it is noted that between the voltage A and voltage B the output across the conductors 72 and 73 is positive and increasing but between voltage B and voltage C the output across the conductors 72 and 73 reverses polarity.

In view of the foregoing it is clear that there has been provided herein a substantially new and improved voltage regulator of the static type capable of providing a constant maximum output voltage for an input voltage varying from the maximum to a lesser voltage. The arrangement providing this improved operation is completely static and is a loW power consumption device operating With a power transmission efiiciency in excess of Accordingly, the voltage regulator in accordance with the invention is not only efiicient and a low maintenance device, but it is also compact and of a low cost per kilowatt of power regulated.

It is understood that the arrangements described herein are exemplary of the principles of the invention and that variations and modifications may be made therein. It is intended to cover in the appended claims all such variations and modifications as fall within the true spirit and scope of this invention.

What is claimed is:

1. A voltage regulator for maintaining a predetermned output voltage to a load from a variable voltage alternat ing current source comprising: a transformer including a primary Winding and a secondary winding; means connecting said secondary Winding in a series loop with said load and said alternating current source; means connecting said primary Winding in parallel across said secondary Winding and said load; first gate means for bypassing said primary winding; second gate means for causing conduction through said primary Winding; first switch means operative during the first half of each half cycle of the alternating current voltage for closing said first gate means and bypassing said primary winding; voltage sensor means responsive to the output voltage being less than said predetermined voltage for providing a corresponding control signal; and second switch means selectively operated by said control signal for closing said second gate means during the last half of each half cycle of the alternating current voltage for a period determined by said control signal, whereby a voltage is developed in said transformer secondary Winding corresponding to the amount said out put voltage is less than said predetermined voltage.

2. A voltage regulator for maintaining a predetermined output voltage to a load from a variable voltage alternating current source comprising: a transformer ineluding a primary Winding and a secondary winding; means connecting said secondary Winding in a series loop with said load and said alternating current source; means connecting said primary winding in parallel across said secondary Winding and said load; first gate means for bypassing said primary winding; second gate means for causing conduction through said primary winding; first switch means operative during the first half of each half cycle of the alternating current voltage for closing said first gate means and bypassing said primary winding thereby to prevent loading of said series loop by said transformer; voltage sensor means responsive to the output voltage being less than said predetermined voltage for providing a corresponding control signal; and second switch means selectively operated by said control signal during the last half of each half cycle of the alternating current voltage for closing said second gate means for a period determined by said control signal whereby a voltage corresponding to the amount said'output voltage is less than said predetermined voltage is developed in said transformer secondary winding and added to the voltage in the loop thereof.

.3. A voltage regulator for maintaining a predetermined output voltage to a load from a variable voltage alternating current source comprisingz a transformer including a primary winding and a secondary Winding; means connecting said secondary winding in a series loop with said load and said alternating current source; a first bidirectional gate, a second bidirectional gate, means connecting said primary winding in series with said second gate across said secondary winding and said load; means connecting said first bidirectional gate across said primary winding and said second gate means, first switch means operative during the first half of each half cycle of the alternating current voltage for closing said first gate so as to bypass said primary winding during such periods; voltage sensor means responsive to the output voltage being less than said predetermined voltage for providing a corresponding control signal, and second switch means selectively operated by said control signal during the last half of each half cycle of the alternating current voltage for closing said second gate means for a period determined by said control signal whereby a voltage corresponding to the amount said output voltage is less than said predetermined voltage is developed in said transformer secondary winding and added to the voltage in the loop thereof.

4. A voltage regulator for applying a preselected output voltage to a load from a source that supplies an input voltage subject to variations; which regulator comprises a transformer; a solid state switching circuit for selectively connecting said transformer between said source and said load so that a substantially constant R.M.S. output voltage is applied to said load notwithstanding input voltage variations; said solid state switching circuit includa first pair'of normally conducting semiconductor devices and a second pair of semiconductor devices that are selectively rendered conductive to alter the circuit connection of said transformer and said source to thereby compensate for input voltage variations; a voltage sensing circuit connected between said transformer and said load for producing an error voltage signal when the output voltage deviates from the preselected value; and a control circuit connected to said solid state switching circuit and to said voltage sensing circuit; said control circuit including means responsive to said error voltage signal from said sensing circuit for rendering said second pair of semiconductor devices conductive so that said transformer becomes connected to said source to compensate for the deviation of the output voltage from the preselected value within a time interval corresponding to the period of onehalf cycle of the applied input voltage.

5. A voltage regulator in accordance with claim 4 wherein said semiconductor devices employed in said solid state switching circuit are silicon controlled rectifiers.

References Cited by the Examiner UNITED STATES PATENTS 3,018,431 1/62 Goldstein 323-45 3,065,399 11/62 McNamce 32386 X 3,070,743 12/62 Harper 323-86 X 3,129,380 4/64 Lichowsky 323--45 MAX L. LEVY, Primary Examiner. 

1. A VOLTAGE REGULATOR FOR MAINTAINING A PREDETERMINED OUTPUT VOLTAGE TO A LOAD FROM A VARIBLE VOLTAGE ALTERNAING CURRENT SOURCE COMPRISING: A TRANSFORMER INCLUDING A PRIMARY WINDING AND A SECONDARY WINDING; MEANS CONNECTING SAID SECONDARY WINDING IN A SERIES LOOP WIT SAID LOAD AND SAID ALTERNATING CURRENT SOURCE; MEANS CONNECTING SAID PRIMARY WINDING IN PARALLEL ACROSS SAID SECONDARY WINDING AND SAID LOAD; FIRST GATE MENS FOR BYPASSING SAID PRIMARY WINDING; SECOND GATE MEANS FOR CAUSING CONDUCTION THROUGH SAID PRIMARY WINDING; FIRST SWITCH MEANS OPERATIVE DURING THE FIRST HALF OF EACH HALF CYCLE OF THE ALTERNATING CURRENT VOLTAGE FOR CLOSING SAID FIRST GATE MEANS AND BYPASSING SAID PRIMARY WINDING; VOLTAGE SENSOR MEANS RESPONSIVE TO THE OUTPUT VOLTAGE BEING LESS THAN SAID PREDETERMINED VOLTAGE FOR PROVIDING A CORRESPONDING CONTROL SIGNAL; AND SECOND SWITCH MEANS SELECTIVELY OPERATED 